Resources

Links about developing for the PSP

• PPSSPP on GitHub
• PPSSPP Development Wiki
• PSP Dev Wiki
• forums.ps2dev.org Also has PSP information.
• PSP Homebrew Community Discord (invite link)
• Minimalist PSP SDK for Windows
• PSP Archive - a website about emulation on the PSP

Useful reporting links

These are links to report.ppsspp.org, where we collect automatic bug reports.

• Shader compilation errors

General programming resources

This is just a collection of interesting things.

Floating point tricks

• UNORM and SNORM to float, hardware edition
• Exact UNORM8 to float

Software optimization

• Agner's Software Optimization Resources
• The most efficient way to do nothing (optimize sleeps in RPCS3)

Rasterization

• Optimizing software occlusion culling / rasterization Blog series by Fabian.
• Rasterizer Notes by nlguiellemot

Meshes

• Half-edge based mesh representations

SIMD resources

SSE gap filling

• SSE - mind the gap!
• SSE sign extension tricks

AVX2 and AVX-512

• Why is AVX-512 useful for RPCS3? (by whatcookie)
• No, AVX-512 is power-efficient in RPCS3 (also by whatcookie)
• Zen5 AVX-512 benchmarking
• MNIST in AVX-512 assembly
• AVX-512 use cases
• The least interesting thing is the 512bit width
• Searching with AVX-512
• Old MS AVX tutorial
• Vector filtering, AVX2 vs AVX-512
• Mask register details on Intel

NEON tricks

• Porting SSE movemask optimizations to ARM64 NEON (magic line: uint64_t bitfields = vget_lane_u64(vreinterpret_u64_u8(vshrn_n_u16(mask, 4)), 0);)
• Coding for NEON - tutorial series from 2013
• NEON vs SSE

When can you start require feature X?

x86-64 CPUs that do not support SSSE3

SSSE3 has the nice instruction pshufb, which is useful for various format conversion operations and a lot more. There are very few x86-64 CPUs left that do not support SSSE3.

Vendor	Models Lacking SSSE3	Notes
AMD	K8 family only (first-gen AMD64): • Athlon 64 • Opteron 1xx/2xx/8xx • Turion 64 • Sempron (AMD64 variants)	Produced ~2003–2007. All Phenom (K10) and later support SSSE3.
Intel	Pre-Penryn Core era: • Early Core Solo/Duo (Yonah – mostly 32-bit) • Some first-gen Core 2 (early Merom/Conroe steppings)	SSSE3 widely deployed starting with Core 2 refresh / Penryn (~2006–2007).
Via	Early VIA Nano	Very rare in the wild.

SSE4.2 is also useful, but there are still some CPUs around that don't support it, so we probably don't want to require it.

x86-64 CPUs that do not support SSE4.2

(latest non-supporting generations)

Vendor	Last Generation Without SSE4.2	Models / Examples	Notes
Intel	Penryn (Core 2 Refresh, ~2007)	Core 2 Duo E8xxx / T9xxx, Core 2 Quad Q9xxx, Xeon 51xx / 53xx	Penryn has SSE4.1 only, no SSE4.2. SSE4.2 starts with Nehalem (Core i7-900 series, 2008).
AMD	Phenom II / K10 (~2008–2010)	Phenom II X4/X6, Athlon II, Opteron 23xx/83xx	K10 supports SSE4a only (not SSE4.1/4.2). Proper SSE4.2 starts with Bulldozer (FX-8000 / Opteron 6200, 2011).
VIA	Early VIA Nano	VIA Nano 2000-series	Later Nano C-series implements SSE4.2-like crypto/string ops; early ones do not.
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